(1) Field of the Invention
The present invention relates to: a method of controlling an information processing device which includes a processor having a cache memory, and a clock supplying unit which supplies a clock signal to the processor; an information processing device; a program; and a program converting method.
(2) Description of the Related Art
As a conventional technology related to controlling electric power consumption of an information processing device, there is a method of controlling a clock frequency of a Central Processing Unit (CPU) in accordance with a cache hit rate (see, for example, Japanese Unexamined Patent Application Publications No. 11-134077, No. 2000-148582 and No. 2005-115769). The information processing device includes hardware which is exclusively used for measuring a cache hit rate of the CPU, and increases the clock frequency of the CPU when the cache hit rate is high, and decreases the clock frequency of the CPU when the cache hit rate is low. With use of this method, it is possible to more effectively reduce electric power consumption, compared to when the clock frequency is constant.
FIG. 1 is a block diagram showing configuration of an information processing device for which the conventional method is used. This information processing device includes a CPU 0101 having a built-in cache, a cache hit rate monitoring circuit 0102, and a clock controlling unit 0103 which controls a clock of the CPU.
The following is a description of operations of the conventional information processing device configured in such manner as described above.
The cache hit rate monitoring circuit 0102 derives a hit rate of the cache equipped in the CPU 0101, and inputs the derived hit rate to the clock controlling unit 0103 as cache hit rate information 0104. The clock controlling unit 0103 controls a frequency of a clock 0105 which is to be supplied to the CPU 0101 in accordance with the cache hit rate information 0104. In doing so, the clock controlling unit 0103 increases the clock frequency of the CPU 0101 when the cache hit rate is high, and decreases the clock frequency of the CPU 0101 when the cache hit rate is low. At the same time, the clock controlling unit 0103 decreases clock frequencies of a bus and a memory connected to the CPU 0101 when the cache hit rate is high, and increases the clock frequencies of the bus and the memory when the cache hit rate is low.
Therefore, the CPU effectively performs its processing when the hit rate is high, and the speed of the bus and the memory is increased when the hit rate is low. In other words, the conventional method attempts to achieve both an improvement in processing efficiency and a reduction in electric power consumption.